SEALSQ Plans Quantum-Resistant Chips, ASIC Design Concept

SEALSQ and its subsidiary IC’Alps will showcase quantum-resistant security products at Electronica 2026 in Munich, including the VaultIC409 secure element, QVault TPM and QASIC post-quantum ASIC design concept. VaultIC409, built on the QS7001 platform, combines a hardware root of trust with acceleration for classical and post-quantum cryptography, including ML-KEM and ML-DSA, and is designed for connected devices such as smart meters and industrial gateways. The company plans a live TLS 1.3 demonstration, with engineering samples expected in the second quarter of 2027; the platform is pursuing Common Criteria EAL5+ certification. QVault TPM stores post-quantum and traditional cryptographic keys in hardware, while support in wolfSSL’s wolfTPM stack gives developers access through a widely used interface. QASIC is presented as a custom-chip design approach incorporating security and post-quantum features for markets including automotive, medical and industrial applications, and SEALSQ will also join NXP and Infineon for a discussion on industrial security.